The allocation of cores is no longer enough when tenants compete for L3. AMD is pushing QoS to the global level with Zen 6 to regulate bandwidth and privileges at the processor level.
AMD Zen 6 PQOS: Cross-domain bandwidth control
AMD details three PQOS additions for Zen 6: Global Bandwidth Enforcement (GLBE), Global Slow Bandwidth Enforcement (GLSBE) et Privilege-Level Zero Association (PLZA). Objective: finely control the behavior of the memory hierarchy and execution privileges on large groups of logical processors.
G.L.B.E allows a common external L3 bandwidth cap for groups of cores going beyond the boundaries of traditional QoS Domains. These groups form a “GLBE Control Domain” where Classes of Service (CoS) share a single limit, overcoming previous implementations confined to the perimeter of a single domain.
GLSBE replicates the same principle, but targeted to the memory marked “Slow Memory”. Both mechanisms are exposed via Model-Specific Registers, with sufficient granularity for policies differentiated by CoS or by extended logical sets.
PLZA: priority CPL=0 and resource monitoring
PLZA introduces automatic association of zero level privileges (CPL=0) to a specific CoS or RMID. Where PQOS identifiers remained tied to the logical thread, hardware can now override this association whenever a core executes highly privileged code, whether the kernel or a hypervisor with SVM.
Direct consequence: resource limits and telemetry can be imposed on the system code independently of the user configuration of the thread, which facilitates the isolation of critical loads and the readability of monitoring on shared hosts.
Impacts for hosting and cloud
GLBE and GLSBE simplify bandwidth policing across heterogeneous vCPU clusters, avoiding side effects between tenants beyond a single L3 domain. PLZA, for its part, facilitates the application of budgets dedicated to the kernel and hypervisors, with limits separated from guest workloads.
These building blocks bring hardware QoS closer to the current needs of large-scale multi-tenancy, where L3 contention and “slow” memory is often the hidden variable. They should reduce inter-VM variability and smooth SLOs without overly complicating the software layer.
Source : TechPowerUp
