EPYC Zen 6 samples already display DDR5-8000. Enough to suggest an aggressive memory platform despite still heterogeneous readings.
AMD EPYC Venice: first DDR5-8000 readings and African platforms
Several OpenBenchmarking entries show “Congo,” “Kenya,” and “Nigeria” systems – codenames for the EPYC Venice platforms – running DDR5-8000. We note a 192-core Congo with 8 to 64 GB DDR5-8000, a 128-core Kenya with 2 to 128 GB DDR5-8000, and a two-socket Nigeria with two 64-core samples also reporting DDR5-8000.
The consistency is not total at this stage. Other pages list DDR5-6400, including a 64-core Congo, a dual-socket Nigeria with two 128-core samples, and another dual-socket Nigeria with two 192-core samples. The whole thing looks like a platform bring-up phase rather than specifications finals.
Zen 6, TSMC N2 and targeted memory bandwidth
AMD has confirmed the essentials: Venice is the 6th generation EPYC under Zen 6, scheduled for launch in 2026, and the first HPC product mounted on the TSMC N2 process. The Helios reference associated with Venice announces up to 256 cores and up to 1.6 TB/s of memory bandwidth.
AMD and Samsung are working together on high-performance DDR5 for this generation, which is consistent with the visible DDR5-8000 readings, although AMD has not made this frequency official as a series specification. At this stage, nothing indicates a definitive prioritization of the Congo, Kenya and Nigeria platforms beyond the configurations observed.
If DDR5-8000 is confirmed in production, the 1.6 TB/s objective will become credible without resorting to exotic memory, with a direct impact on bandwidth-sensitive HPC and AI loads. Positioning in 2026 on TSMC N2 and a ceiling of 256 cores would also indicate a clear competitive level compared to x86 and ARM offers of the same window.
Source : VideoCardz
